Semiconductor integrated circuit and method for manufacturing the same

ABSTRACT

An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor integrated circuitdevices and methods for manufacturing the same and, more particularly,to a technique effectively used for semiconductor integrated circuitdevices having a static memory (SRAM; static random access memory) andlogic circuits:

BACKGROUND OF THE INVENTION

[0002] AN-SRAM is a memory device utilizing a flip-flop circuit as amemory element, the bi-stable states of which are respectively stored inassociation with “1” and “O” levels of information, and it ischaracterized in that it is easy to use because it requires no refreshoperation, unlike a DRAM (dynamic random access memory). The flip-flopcircuit is formed by two inverter circuits. The output of one of theinverter circuits is electrically connected to the input of the otherinverter circuit, and the output of the other inverter circuit iselectrically connected to the input of the first inverter circuit. Eachof the inverter circuits includes a driving transistor that contributesto the storage of information and a load element for supplying a powersupply voltage to the driving transistor. Further, the flip-flop circuitis provided between a pair of data lines, and a structure is employed inwhich a transfer transistor is interposed between the flip-flop circuitand each of the data lines to electrically connect or electricallydisconnect the flip-flop circuit and the data lines.

[0003] Memory cells for such an SRAM are categorized into highresistance load type cells and CMIS (complementary metal insulatorsemiconductor) type cells depending on the load elements in the memorycells. In the high resistance load type, a polysilicon resistor is usedas a load element. In this case, since the resistor occupies a smallarea and can be overlaid on a driving transistor or the like, the totalarea of a memory cell region can be minimized to provide a largecapacity. On the other hand, a p-channel type MISFET is used as a loadelement in the CMIS type, which minimizes the power consumption of thesame. Some CMIS type memory cells have a so-called TFT (thin filmtransistor) structure in which two polysilicon layers are provided on alayer above of an n-channel type MOSFET serving as a driving transistorand in which a p-channel type MOSFET to be used as a load element isformed by the polysilicon layers to also reduce the total area of thememory cell region.

[0004] For example, a semiconductor integrated circuit device having anSRAM is described in Japanese Patent Laid-Open No. 167655/1996. In orderto integrate high performance logic circuits and a highly integratedCMOS type memory cell array in the same chip without increasing thecomplexity of the manufacturing processes, a structure is disclosed inwhich logic circuits are formed by a top channel type n-channel MOSFETand p-channel MOSFET and in which a memory cell is formed by directlyconnecting the gate electrodes of the n-channel MOSFET and p-channelMOSFET having the same conductivity.

[0005] International Publication No. W97/38444 discloses an adjustmenton the threshold voltage of a transfer transistor of an SRAM.

SUMMARY OF THE INVENTION

[0006] The inventor has found that the above-described technique forsemiconductor integrated circuit devices having an SRAM has thefollowing problems.

[0007] Specifically, semiconductor integrated circuit devices having anSRAM have had a problem in that no sufficient attention has been paid tothe need for setting separate threshold voltages for elements formingmemory cells and other elements that arises from the trend toward higherspeeds, lower power consumption and higher integration of elements andin that semiconductor integrated circuit devices have operational faultsin the memory circuit which have not been revealed in the past when theyare manufactured giving consideration only to ease of manufacture. Forexample, semiconductor integrated circuit devices having an SRAM andlogic circuits provided on the same semiconductor substrate have beensubjected to increasing efforts toward logic circuits and SRAMperipheral circuits (hereinafter referred to “logic circuits and thelike”) having higher speeds and toward lower power consumption andhigher integration of the semiconductor integrated circuit devices as awhole. Efforts are being made to decrease the threshold voltage of thelogic circuits and the like in order to increase the speed of the same.However, when the threshold voltages of a logic circuit and the like anda memory circuit are set at the same step taking only factors such asease of manufacture into consideration without considering thesignificant trend toward increased speed of a logic circuit and the likeand lower power consumption of a semiconductor integrated circuitdevice, the noise margin of memory cells in the memory circuit isreduced although the operating speed of the logic circuit and the likecan be improved. Studies made by the inventors have revealed that thiscauses operational faults of the memory circuit which have not occurredeven with the threshold voltages of the logical circuit and the like andthe memory circuit set at the same step.

[0008] It is an object of the invention to provide a technique whichmakes it possible to improve the operational margin of a memory of asemiconductor-integrated circuit device having an SRAM.

[0009] It is another object of the invention to provide a techniquewhich makes it possible to reduce the power consumption of asemiconductor integrated circuit device having an SRAM.

[0010] It is an object of the invention to provide a technique whichmakes it possible to improve the margin of writing to a memory of asemiconductor integrated circuit device having an SRAM.

[0011] The above and other objects and novel features of the inventionwill be apparent from the description provided in this specification andthe accompanying drawings.

[0012] Typical aspects of the invention disclosed in this specificationcan be briefly described as follows.

[0013] A semiconductor integrated circuit device according to theinvention has a plurality of first field effect transistors forming amemory cell of an SRAM and a second field effect transistor provided ona semiconductor substrate, in which the threshold voltage of at leastone first field effect transistor among said plurality of first fieldeffect transistors is relatively higher than the threshold voltage ofsaid second field effect transistor.

[0014] A method of manufacturing a semiconductor integrated circuitdevice according to the invention, and having a plurality of first fieldeffect transistors forming a memory cell of an SRAM and a second fieldeffect transistor formed on a semiconductor substrate, includes animpurity introduction step for selectively introducing a first impurityinto a region to form at least one of said first field effecttransistors on said semiconductor substrate in order to set thethreshold voltage of said at least one first field effect transistoramong said plurality of first field effect transistors relatively higherthan the threshold voltage of said second field effect transistor.

[0015] A method of manufacturing a semiconductor integrated circuitdevice according to the invention, and having a plurality of first fieldeffect transistors forming a memory cell of an SRAM and a second fieldeffect transistor formed on a semiconductor substrate, includes a stepof selectively introducing nitrogen into the region to form said secondfield effect transistor on said semiconductor substrate and thereafterforming a gate insulation film on said semiconductor substrate in orderto set the threshold voltage of said at least one first field effecttransistor among said plurality of first field effect transistorsrelatively higher than the threshold voltage of said second field effecttransistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a diagram showing a configuration of circuit blocks of asemiconductor integrated circuit device, which represents a mode forcarrying out the invention.

[0017]FIG. 2 is a circuit diagram of a memory cell in an SRAM of thesemiconductor integrated circuit device in FIG. 1.

[0018]FIG. 3 is a plan view of a major part of a memory cell region ofthe SRAM of the semiconductor integrated circuit device in FIG. 1.

[0019]FIG. 4 is a plan view of a layer above that shown in FIG. 3 in thememory cell region of the SRAM of the semiconductor integrated circuitdevice in FIG. 1.

[0020]FIG. 5 is a sectional view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step of the same.

[0021]FIG. 6 is a plan view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step subsequentto that shown in FIG. 5.

[0022]FIG. 7 is a sectional view of a major part of the memory cellregion of the SRAM of the semiconductor integrated circuit device inFIG. 1 at a manufacturing step subsequent to that shown in FIG. 6.

[0023]FIG. 8 is a sectional view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step subsequentto that shown in FIG. 7.

[0024]FIG. 9 is a sectional view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step subsequentto that shown in FIG. 8.

[0025]FIG. 10 is a sectional view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step subsequentto that shown in FIG. 9.

[0026]FIG. 11 is a sectional view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step subsequentto that shown in FIG. 10.

[0027]FIG. 12 is a sectional view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step subsequentto that shown in FIG. 11.

[0028]FIG. 13 is a sectional view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step subsequentto that shown in FIG. 12.

[0029]FIG. 14 is a sectional view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step subsequentto that shown in FIG. 13.

[0030]FIG. 15 is a sectional view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step subsequentto that shown in FIG. 14.

[0031]FIG. 16 is a sectional view of a major part of the semiconductorintegrated circuit device in Fig. at a manufacturing step subsequent tothat shown in FIG. 15.

[0032]FIG. 17 is a sectional view of a major part of the semiconductorintegrated circuit device in FIG. 1 at a manufacturing step subsequentto that shown in FIG. 16.

[0033]FIG. 18 is a table which illustrates SNM characteristics of thesemiconductor integrated circuit device in FIG. 1.

[0034]FIG. 19 is a table which illustrates SNM characteristics of atechnique studied by the inventor for comparison to explain the effectsof the semiconductor integrate circuit device in FIG. 1.

[0035]FIG. 20 is a graph showing the relationship between a thresholdvoltage and an SNM of a driving field effect transistor in the SRAM ofthe semiconductor integrated circuit device in FIG. 1.

[0036]FIG. 21 is a plan view of A major part of memory cells of an SRAMof a semiconductor integrated circuit device, which is another mode forcarrying out the invention at a manufacturing step of the same.

[0037]FIG. 22 is a plan view of a major part of memory cells of an SRAMof a semiconductor integrated circuit device, which represents stillanother mode for carrying out the invention at a manufacturing step ofthe same.

[0038]FIG. 23 is a sectional view of a major part of a semiconductorintegrated circuit device which is another mode for carrying out theinvention at a manufacturing step of the same.

[0039]FIG. 24 is a sectional view of a major part of the semiconductorintegrated circuit device at a manufacturing step subsequent to thatshown in FIG. 23.

[0040]FIG. 25 is a sectional view of a major part of the semiconductorintegrated circuit device at.a manufacturing step subsequent to thatshown in FIG. 24.

[0041]FIG. 26.is a graph of SNM characteristics of an SRAM.

[0042]FIG. 27 is a graph of SNM characteristics of a semiconductorintegrated circuit device studied by the inventor.

[0043]FIG. 28 is a graph showing the relationship between the draincurrents of a transfer field effect transistor and a field effecttransistor for load resistance forming an SRAM of a semiconductorintegrated circuit device studied by the inventor.

[0044]FIG. 29 is a graph showing the relationship between the draincurrents of a transfer field effect transistor and a field effecttransistor for load resistance forming an SRAM of a semiconductorintegrated circuit device studied by the inventor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0045] Modes for carrying out the invention will now be described indetail with reference to the drawings (parts having like functions aregiven like reference numbers throughout the drawings and will not bedescribed repeatedly).

[0046] Embodiment 1:

[0047]FIGS. 1 through 4 are illustrations which will be referred to forexplaining an example of the structure of a semiconductor integratedcircuit device according to the invention. FIGS. 5 through 17 aresectional views of major parts of the semiconductor integrated circuitdevice during manufacturing steps which will be used for explaining amethod of manufacturing the semiconductor integrated circuit device ofFIG. 1. FIG. 18 is an illustration used for explaining the effects ofthe present mode for carrying out the invention. FIG. 19 illustrates atechnique studied by the inventor to explain the effects of the presentmode for carrying out the invention. FIG. 20 is an illustration forexplaining the effects of the present mode for carrying out theinvention.

[0048] In the context of the technical description presented herein,when it is stated that “a threshold voltage (hereinafter abbreviated as“Vth′) is high”, it means that there is an intentional increase of Vthbeyond an increase in Vth attributable to a dimensional difference inthe channel width or the like. Further, in the context of the technicaldescription, Vth represents a gate voltage that appears when there is aflow of current of 1.0 μA per a unit channel width (e.g., per a width of1 μm).

[0049] According to the technical principle of the invention, in asemiconductor integrated circuit device having MISFETs (metal insulatorsemiconductors) constituting an SRAM (static random access memory) andother MISFETs constituting a logic circuit, such as a microprocessor(CPU) provided on the same semiconductor substrate, as shown in FIG. 1,a separate value of Vth is set for each of the MISFETs forming an SRAMand other MISFETs. This is based on the results of studies made by theinventor, as will be described below. For example, random bit faultshave occurred in memory cells of an SRAM as a result of a trend towardhigher operational speeds and lower power consumption (i.e., lower powersupply voltages) of semiconductor integrated circuit devices having anSRAM and a logic circuit and the like on the same semiconductorsubstrate and toward higher degrees of integration of elements. Uponmaking certain studies, the inventor discovered a fault mode in whichsuch memory cells have a small operational margin as a major cause ofsuch faults. A further study indicated that potential problems had beenactualized with the trend toward higher speeds and lower power supplyvoltages of such semiconductor integrated circuit devices or higherdegrees of integration of elements.

[0050] Specifically, in order to increase the speed of the logic circuitand the like of a semiconductor integrated circuit device, as describedabove, Vth is normally decreased. However, when Vth of the logic circuitand the like and the memory circuit is set at the same step, taking onlythe aspects of ease of manufacture and the like into considerationwithout considering the significant trend toward higher speeds of logiccircuits and the like, lower power consumption of semiconductorintegrated circuit devices or higher degrees of integration of elements,the Vth of MISFETs in the memory cell region is also decreased to causeoperational faults in the memory which have not been revealed even withthe Vth of the logic circuit and the like and the memory circuit set atthe same step.

[0051] Especially, when an isolation structure (shallow trenchisolation) based on the LOCOS (local oxidation of silicon) process isreplaced by a trench type buried isolation structure in order to achievea higher degree of integration of elements, the MISFETs exhibit reversenarrow channel characteristics which result in a low Vth. If the Vth ofthe logic circuit and the like and the memory circuit is set at the samestep without considering the same and taking only the ease ofmanufacture into consideration, the Vth of the MISFETs in the memorycell region significantly decreases to cause operational faults in saidmemory which have not been revealed.

[0052]FIG. 26 provides waveforms showing the operational stability of amemory cell, e.g., waveforms obtained by plotting a voltage at one ofthe nodes of a memory cell in A 6 MISFET type SRAM relative to a voltageapplied to the other node in an overlapping relationship (transfercurves). A region where the curves overlap each other represents amargin for noise, and the length of such an overlapping region (theregion which is longest in the direction at an 5 angle of 45°) is astatic noise margin (SNM). The greater the overlap (i.e., the greaterthe SNM), the higher will be the stability at which the memory operates.However, when the Vth of a MISFET for driving a memory cell is as low asthe Vth of the logic circuit and the like, particularly with the Vth ofthe logic circuit and the like and the memory circuit set at the samestep, the SNM is small as shown in FIG. 27, which makes the operation ofthe memory unstable.

[0053]FIGS. 28 and 29 are graphs showing the results of measurement ofthe drain currents of a transfer. MISFET for a memory cell and a MISFETto be used as load resistance. Those figures indicate that a read faultoccurs at the transfer MISFET when the Vth is too high or too low andthat a write fault occurs at the MISFET used as a load resistance whenthe Vth is too low. That is, the present inventor has found that it ispreferable to set not only the Vth of a MISFET for driving a memory cellbut also the Vth of the transfer MISFET and the MISFET used as a loadresistance separately from the Vth of the logic circuit and the like,depending on the operational environment, operating conditions and thelike.

[0054] Next, a description will be made concerning the structure of asemiconductor integrated circuit device according to the present modefor carrying out the invention with reference to an application of atechnical principle of the invention to a microprocessor having an SRAMfor a cache memory as an example.

[0055]FIG. 1 shows a major circuit block provided in a semiconductorchip IC according to the present mode for carrying out the invention.Specifically, the semiconductor chip IC includes, for example, aninput/output circuit I/0, logic circuits, such as a microprocessor(CPU), 2A through 2C, an SRAM for a cache memory, a phase locked loopcircuit PLL, a clock pulse generation circuit CPG and the like. Thepower supply voltage of a high potential side of this semiconductorintegrated circuit device is, for example, 2.5 V or less. The minimumgate length of MISFETs forming this semiconductor integrated circuitdevice is, for example, about 0.25 μm. For example, the Vth of MISFETs,which must be fast, is 0.25 V or less.

[0056] For example, a plurality of 6 MISFET (metal insulatorsemiconductor field effect transistor) type memory cells MC as shown inFIG. 2 are provided in a memory cell region of the SRAM. The memorycells MC are provided in the vicinity of the intersections of a pair ofcomplementary data lines DL1, DL2 (DL) and a word line WL and include apair of driving MISFETs Qd1, Qd2 (Qd; first field effect transistor), apair of MISFETs QL1, QL2 (QL; first field effect transistor) used as aload resistance and a pair of transfer MISFETs Qt1, Qt2 (Qt; first fieldeffect transistor). The pair of complementary data lines DL1, DL2transmit signals which are inversions of each other.

[0057] Said pair of driving MISFETs Qd1, Qd2 and the pair of MISFETsQL1, QL2 used as a load resistance form a flip-flop circuit. Theflip-flop circuit is a memory cell′. which stores one bit of information(“1” or “0”) and which is electrically connected to a power supply Vddat a high potential side at one end thereof (the side of the MISFETsQL1, QL2 used as load resistance) and is electrically connected to apower supply GND at a ground side at the other end (the side of thedriving MISFETs Qd1, Qd2). For example, the voltage of the power supplyvdd at the high potential side is about 1.8 V, and the voltage of thepower supply GND at the ground side is 0 V.

[0058] The pair of transfer MISFETs Qt1, Qt2 are switching elements forelectrically connecting and disconnecting the flip-flop circuit to andfrom the data lines DL1, DL2 and are interposed between input and outputterminals of the flip-flop circuit (accumulation nodes N1, N2) and thedata lines DL1, DL2, respectively. The gate electrodes of the pair oftransfer MISFETs Qt1, Qt2 are electrically connected to the word lineWL.

[0059]FIGS. 3 and 4 show plan views of a major part of the memory cellregion. While FIG. 4 illustrates the same position as that in FIG. 3 asa plan view, it illustrates first layer wiring above the layer shown inFIG. 3 and second layer wiring as a sectional view.

[0060] A semiconductor substrate 3 is made of, for example, p-typesilicon (Si). P-wells and n-wells to be described later are formed onthe semiconductor substrate 3. Isolation portions 4 are formed on theprinciple surface of the semiconductor substrate 3. Transfer MISFETs Qt,driving MISFETs Qd and MISFETs for load resistance QL are formed inactive regions surrounded by the isolation portions 4. The transferMISFETs Qt and driving MISFETs Qd are constituted by, for example,n-channel MISFETs, and the MISFETs for load resistance QL areconstituted by, for example, p-channel MISFETs. In FIG. 3, NMISrepresents a region where n-channel MISFETs are formed, and PMISrepresents a region where p-channel MISFETs are formed. In-the presentmode for carrying out the invention, the designed channel widths of thedriving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistanceQL are smaller than the designed channel width of MISFETs forming logiccircuits and SRAM peripheral circuits (second field effect transistors).The term “designed” implies the fact that some error may be included.

[0061] The transfer MISFETs Qt include an n-type semiconductor region 5and a gate electrode 6gt; the driving MISFETs Qd include an n-typesemiconductor region 5 and a gate electrode 6gd; and the MISFETs forload resistance QL include a p-type semiconductor region and a gateelectrode 6gL.

[0062] The n-type semiconductor regions 5 are regions where the sourcesand drains of the transfer MISFETs Qt and driving MISFETs Qd are formedand are formed by introducing, for example, phosphorus (P) or arsenic(As) into said p-wells. One of such n-type semiconductor regions 5 is aregion shared by a transfer MISFET Qt and a driving MISFET Qd whichfunctions as wiring to electrically connect both of the MISFETs. Theother n-type semiconductor region 5 of the transfer MISFET Qt iselectrically connected to a data line DL (see FIG. 4) through aconnection hole 8A for the data line. The data lines DL are made of forexample, aluminum, aluminum-silicon-copper alloy or the like and areformed in the second wiring layer. The n-type semiconductor regions 5shared by transfer MISFETs Qt and driving MISFETs Qd are connected tothe gate electrodes 6gdm 6gL of other driving MISFETs Qd and MISFETs forload resistance QL which are to be paired therewith through connectionholes 8B and are electrically connected to first layer wiring 9L (seeFIG. 4). The first layer wiring 9L is made of, for example, aluminum,aluminum-silicon-copper or the like and is connected to one of p-typesemiconductor regions 7 of a load resistance MISFET QL through aconnection hole 8C. The other n-type semiconductor regions 5 of thedriving MISFETs Qd are electrically connected to first layer wiring 9LG(see FIG. 4) for the power supply GND at the low potential side (seeFIG. 2) through connection holes 8D. The other p-type semiconductorregions 7 of the load resistance MISFET QL are electrically connected tofirst layer wiring 9tv (see FIG. 4) for the power supply Vdd at the highpotential side (see FIG. 2) through connection holes 8E.

[0063] The gate electrodes 6gt of the transfer MISFETs Qt areconstituted by a part of word lines WL and are in the form of planarband-shaped patterns extending horizontally in FIG. 3. The gateelectrodes 6gd, 6gL of the driving MISFETs Qd and MISFETs for loadresistance QL are formed in a part of an integral gate pattern A part ofthis gate pattern extends diagonally to gate pattern portions connectingthe gate electrodes 6gd, 6gL and is formed in a planar Y-shapedconfiguration as a whole. The ends of the diagonally extending portionsof the gate pattern are electrically connected to the n-typesemiconductor regions 5 and the first layer wiring 9L through saidconnection holes 8B to function as wiring. One memory cell MC has twogate patterns which are adjacent to each other in the horizontaldirection of FIG. 3. The gate electrodes 6gt, 6gL are formed on a gateinsulation film to be described later and are constituted by, forexample, a single film of low resistance polysilicon, a multi-layer filmformed by providing a silicide layer made of tungsten silicide or thelike on a low resistance polysilicon film or a multilayer film formed byproviding a metal film such as tungsten on a low resistance polysiliconfilm with titanium nitride, tungsten nitride or the like interposedtherebetween.

[0064] A description will now be made with reference to FIGS. 5 through17 to explain an example of a method of manufacturing a semiconductorintegrated circuit device according to the present mode for carrying outthe invention. Throughout the drawings, I/0-NMIS represents a regionwhere an n-channel type MISFET for forming an input/output circuit isformed; I/0-PMIS represents a region where a p-channel type MISFET forforming the input/output circuit is formed; logic-NMIS represents aregion where an n-channel type MISFET for a logic circuit is formed; andlogic-NMIS represents a region where a p-channel type MISFET for thelogic circuit is formed. Examples of regions where driving MISFETs andMISFETs for load resistance are formed are shown in the memory cellregion shown in FIGS. 5 through 17.

[0065] For example, as shown in FIG. 5, a p-type semiconductor substrate(a semiconductor wafer at this stage) 3 having a specific resistance onthe order of 10 gcm is first subjected to wet oxidation at 800° C. toform a thin silicon oxide film 10 having a thickness of about 10 nm onthe surface thereof and, thereafter, a silicon nitride film 11 having athickness of about 200 nm is deposited thereon using the CVD (chemicalvapor deposition) method. The silicon oxide film 10 is formed tomoderate stress that acts on the semiconductor substrate 3 when siliconoxide films embedded in element isolating grooves are sintered(vitrified) at a later step. Since the silicon nitride film 11 has theproperty of resisting oxidation, it is used as a mask to preventoxidation of the substrate surface thereunder (active region).

[0066] Subsequently, the silicon nitride film 11, silicon oxide film 10and semiconductor substrate 3 are subjected to dry etching using aphotoresist film as a mask to form isolation grooves 4 a having a depthof about 300 to 400 nm on the semiconductor substrate 3 in elementisolation regions. The isolation grooves 4a may be formed by performingdry etching of the silicon nitride film 11 using a photoresist film as amask, removing the photoresist film, and thereafter performing dryetching of the silicon oxide film 10 and semiconductor substrate 3 usingthe patterned silicon nitride film 11 as a mask.

[0067] Next, in the present mode for carrying out the invention, aprocess (hereinafter referred to as “first process) as described belowis performed to set the Vth of driving MISFETs, transfer MISFETs andMISFETs for load resistance forming memory cells of an SRAM, relativelyand intentionally higher than the Vth of predetermined MISFETs of SRAMperipheral circuits and logic circuits.

[0068] The photoresist film for forming the isolation grooves is firstremoved and, in order to set the Vth of the driving MISFETs and transferMISFETs relatively and intentionally higher, a photoresist pattern 12Ais formed such that regions where the driving MISFETs Qd and transferMISFETs Qt are to be formed are exposed on the semiconductor substrate 3and such that regions other than them are covered as shown in FIG. 6.FIG. 6 shows the same memory cell region as in FIG. 3. Although elementsand the like have not been formed yet at the stage shown in FIG. 6, theyare shown here for better clarity of the position where the photoresistpattern 12A is formed. Further, the photoresist pattern 12A in FIG. 6 ishatched for better clarity of the drawing. The pattern configuration ofthe photoresist pattern 12A is not limited to that shown here; and, forexample, the pattern may be formed into a configuration which exposesthe regions to form the driving MISFETs Qd and transfer MISFETs Qt andalso exposes the regions of n-channel type MISFETs formed on thesemiconductor substrate 3, especially regions to form MISFETs for whichany leakage current between the source and drain must be suppressed, andwhich covers other regions.

[0069] Subsequently, for example, boron difluoride (BF2) ions areimplanted into the semiconductor substrate 3 using the photoresistpattern 12A as a mask. This is carried out under conditions as describedbelow, although they are not a limiting aspect of the invention.Specifically, the ion implantation energy is about 40 keV; the dose isabout 1×10¹²/CM²; and ion implantation angle is about 10 degrees. Theions are implanted at an angle in order to increase the Vth of theactive region as a whole by introducing the impurity ions into the sidesof the isolation grooves 4 a. The ion implantation angle is the angle atwhich the impurity ions impinge upon the principle surface of the.semiconductor substrate 3.

[0070] Next, after removing the photoresist pattern 12A, a photoresistpattern 12B is formed which exposes the regions to form the MISFETs forload resistance QL on the semiconductor substrate 3-as shown in FIG. 7in order to relatively and intentionally increase the Vth of the MISFETsfor load resistance QL, and which covers other regions. FIG. 7 alsoshows the same memory cell region as in FIG. 3. Although elements andthe like have not been formed yet at this stage, they are shown here toclearly show the position where the photoresist pattern 12B is formed.Further, the photoresist pattern 12B in FIG. 7 is also hatched forbetter clarity of the drawing. The pattern configuration of thephotoresist pattern 12B is not limited to that shown here and, forexample, the pattern may be formed into a configuration which exposesthe regions to form the MISFETs for load resistance QL and also exposesthe regions of p-channel type MISFETs formed on the semiconductorsubstrate 3, especially regions to form MISFETs for which any leakagecurrent between the source and drain must be suppressed, and whichcovers other regions.

[0071] Subsequently, for example, phosphorus (P) ions are implanted intothe semiconductor substrate 3 using the photoresist pattern 12B as amask. This may be carried out under the same conditions as for theintroduction of the impurity to relatively and intentionally increasethe Vth of the driving MISFETs Qd as described above, although this isnot a limiting aspect of the invention. Thereafter, the photoresistpattern 12B is removed.

[0072] The order of the process of introducing an impurity to increasethe Vth of the driving MISFETs Qd and the like as described above andthe process of introducing an impurity to increase the Vth of theMISFETs for load resistance QL may be reversed. The Vths of the drivingMISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL arerelatively and intentionally increased by performing such a series ofprocesses.

[0073] After such a first process, in order to remove any damaged layerproduced on the inner walls of the isolation grooves 4 a as a result ofsaid etching, the semiconductor substrate 3 is subjected to dryoxidation at about 1000° C. to form thin silicon oxide films having athickness of about 30 nm on the inner walls of the isolation grooves 4a. Subsequently, as shown in FIG. 8, a silicon oxide film 13 having athickness of about 400 nm on the semiconductor substrate 3 is depositedand, thereafter, the semiconductor substrate 3 is subjected to wetoxidation to perform sintering (vitrification) for improving the qualityof the silicon oxide films 13 embedded in the isolation grooves 4 a. Forexample, the silicon oxide film 13 is deposited using a plasma CVDprocess that utilizes ozone (O₃) and tetraethoxysilane (TEOS) as sourcegases.

[0074] Next, a CVD process is performed to deposit a silicon nitridefilm having a thickness of about 200 nm on the silicon oxide films 13,and the silicon nitride film is thereafter subjected to dry etchingusing a photoresist film as a mask to leave silicon nitride films 14only on isolation grooves 4 a having relatively large areas, e.g.,boundaries between the memory array and the peripheral circuits. Thesilicon nitride films 14 left on the isolation grooves 4 a are formed inorder to prevent a phenomenon (dishing) that occurs when the siliconoxide films 13 in isolation grooves 4 a having relatively large areasare polished to a greater depth than the silicon oxide films 13 inisolation grooves having relatively smaller areas as the silicon oxidefilms 13 are polished and planarized using a chemical mechanicalpolishing (CMP) process at the next step.

[0075] Subsequently, after the photoresist film for patterning thesilicon nitride films 14 is removed, a CMP process is carried out usingthe silicon nitride films 11, 14 as stoppers to polish and leave thesilicon oxide films 13 in the isolation grooves 4 a, thereby forming theisolation portions 4. While a reduction in the Vth of the MISFETsforming memory cells attributable to reverse narrow channelcharacteristics should normally be inevitable because a groove typeisolating structure is employed as a structure for the isolationportions 4, this mode for carrying out the invention is free from such aproblem because it involves said first process or a process to bedescribed later for relatively and intentionally increasing the Vth ofthe MISFETs forming the memory cells.

[0076] Thereafter, the silicon nitride films 11, 14 are removed, and apre-oxidation process is carried out on the semiconductor substrate 3 toform a gate insulation film having a thickness of about 10 nm on thesemiconductor substrate 3. Then, as shown in FIG. 9, a photoresistpattern 12C is formed which exposes the buried regions on the principlesurface of the semiconductor substrate 3 and covers other regions; and,for example, phosphorus ions are implanted into the semiconductorsubstrate 3 using the photoresist pattern 12C as a mask to form ann-type buried region 15 on the semiconductor substrate 3. While then-type buried region 15 has not been formed yet at this stage because athermal process for the activation of the impurity and the like has notbeen performed on the semiconductor substrate 3, the region isillustrated here for clarity of the description.

[0077] Next, after removing the photoresist pattern 12C, a photoresistpattern is formed which exposes n-well regions throughout the principlesurface of the semiconductor substrate 3 and covers other regions.

[0078] Subsequently, for example, phosphorus ions are implanted into thesemiconductor substrate 3 using the photoresist pattern as a mask. Twokinds of impurity introduction steps are separately performed here whichare a step of introducing said impurity for forming at least n-wells16NW and a step of introducing said impurity for setting the Vth ofMISFETs formed in n-wells 16NW in regions other than the memory cellregion. Thereafter, the photoresist pattern is removed.

[0079] Next, as shown in FIG. 10, a photoresist pattern 12D is formedwhich exposes p-well regions throughout the principle surface of thesemiconductor substrate 3 and covers other regions. Subsequently, forexample, boron or boron difluoride ions are implanted into thesemiconductor substrate 3 using the photoresist pattern 12D as a mask.Two kinds of impurity introduction steps are separately performed herewhich are a step of introducing said impurity for forming at leastp-wells 16PW and a step of introducing said impurity for setting the Vthof MISFETs formed in p-wells 16PW in regions other than the memory cellregion. Thereafter, the photoresist pattern 12D is removed.

[0080] After said step of introducing the impurity for wells and thelike, a process (hereinafter referred to as a “second process”) asdescribed below may be performed instead of the above-described firstprocess to relatively and intentionally increase the Vth of said drivingMISFETs, transfer MISFETs and MISFETs for load resistance beyond the Vthof predetermined MISFETs of the SRAM peripheral circuits and logiccircuits.

[0081] First, in order to set the Vth of the driving MISFETs andtransfer MISFETs relatively and intentionally higher, said photoresistpattern 12A is formed as shown in FIG. 6 (or a photoresist pattern as amodification thereof). Although elements and the like have not beenformed yet also at this stage, they are shown here for better clarity ofthe position where the photoresist pattern 12A is formed.

[0082] Subsequently, for example, boron difluoride (BF₂) ions areimplanted into the semiconductor substrate 3 using the photoresistpattern 12A as a mask. This is carried out under conditions as describedbelow, although they are not a limiting aspect of the invention.Specifically, the ion implantation energy is about 60 keV; the dose isabout 3×10¹²/cm²; and the ion implantation angle is about 90 degrees(i.e., perpendicular to the principle surface of the semiconductorsubstrate 3).

[0083] Next, after removing the photoresist pattern 12A, saidphotoresist pattern 12B shown in FIG. 7 (or a modification of the same)is formed in order to relatively and intentionally increase the Vth ofthe 10 MISFETs for load resistance QL. Although elements and the likehave not been formed yet also at this stage, they are shown here toclearly show the position where the photoresist pattern 12B is formed.

[0084] Subsequently, for example, phosphorus (P) ions are implanted intothe semiconductor substrate 3 using the photoresist pattern 12B as amask. The conditions may be the same as said conditions for theintroduction of the impurity to relatively and intentionally increasethe Vth of the driving MISFETs Qt and the like in the second processexcept that the ion implantation energy is, for example, about 40 keV,although this is not limiting the invention.

[0085] The order of the process of introducing an impurity to increasethe Vth of the driving MISFETs Qd and the like as described above andthe process of introducing an impurity to increase the Vth of theMISFETs for load resistance QL may be reversed also in this case.

[0086] The Vths of the driving MISFETs Qd, transfer MISFETs Qt andMISFETs for load resistance QL are relatively and intentionallyincreased by performing such a series of processes.

[0087] After such a second process, a thermal process is performed onthe semiconductor substrate 3 to carry out the activation of theimpurity introduced into the semiconductor substrate 3 and the like,thereby forming the n-wells 16NW, p-wells 16PW and n-type buried region15 on the semiconductor substrate 3. The process then proceeds to thestep of forming the gate insulation film and, in this mode for carryingout the invention, the step of forming the gate insulation film may bepreceded by a process as described below (hereinafter referred to as a“third process) which replaces the above-described first process orsecond process to relatively and intentionally increase the Vth of saiddriving MISFETs, transfer MISFETs and MISFETs for load resistance beyondthe Vth of predetermined MISFETs of the SRAM:peripheral circuits andlogic circuits.

[0088] First, a photoresist pattern is formed which exposes regions toform MISFETs whose operating speed must be increased in the regions ofthe peripheral circuits and logic circuits and which covers regions toform MISFETs for which any leakage current between the source and drainmust be suppressed throughout the memory cell region and in the regionsof the peripheral-circuits and logic circuits.

[0089] Subsequently, for example, nitrogen (N) ions are implanted intothe-semiconductor substrate 3 using the photoresist pattern as a mask.This is carried out under conditions as described below, although theyare not a limiting aspect of the invention. Specifically, the ionimplantation energy is about 5 keV; the dose is about 4×10¹²/cm²; andthe ion implantation angle is about 90 degrees.

[0090] It is thus possible to set the Vth of the driving MISFETs,transfer MISFETs and MISFETs for load resistance in the memory cellregion relatively and intentionally higher. The reason for this is asfollows. Specifically) the Vth of a MISFET decreases when nitrogen isincluded in the gate insulation film thereof Further, in a region dopedwith nitrogen, the gate insulation film is nitrised to have increasedanti-oxidation properties and therefore becomes thinner than the gateinsulation film in a region which is not doped with nitrogen. The Vth ofa MISFET whose gate insulation film is formed in a region doped withnitrogen can be made relatively smaller than the Vth of a MISFET whosegate insulation film is formed in a region which is not doped also inthis aspect.

[0091] Since nitrogen is segregated on the interface between the gateinsulation film and the semiconductor substrate 3 in a region doped withnitrogen, an advantage can be obtained in that the reliability of thegate insulation film can be improved. It is known that a reduction inthe thickness of a gate insulation film causes a distortion of theinterface between the gate insulation film and the semiconductorsubstrate 3 attributable to the difference between the thermal expansioncoefficients of the film itself and the semiconductor substrate 3 toinduce the generation of hot carriers. The reason for this is that sucha distortion is moderated by the nitrogen segregated on the interface tothe semiconductor substrate 3. Since the problem of hot carriers isunlikely to occur in a memory cell region, no particular problem occurseven if a memory cell region is not doped with nitrogen.

[0092] While the present mode for carrying out the invention hasreferred to a case wherein said third process is carried out instead ofsaid first process or second process, this is not a limiting aspect ofthe invention and the third process may be carried out in combinationwith the first process or second process.

[0093] After such a third process, the process proceeds to, for example,a step of forming gate insulation films, as will be described below.

[0094] First, an oxidation process for forming the gate insulation filmsof MISFETs having a high withstand voltage formed on the semiconductorsubstrate 3 is performed to form gate insulation films having themaximum relative thickness of, for example, 9 nm or more on theprinciple surface of the semiconductor substrate 3. Subsequently, aphotoresist pattern is formed on the gate insulation film to cover theregion to form the MISFETs having a high withstand voltage and to exposeother regions; and, thereafter, the thick gate insulation film exposedfrom the photoresist pattern is removed and the photoresist pattern isreduced further.

[0095] While the process normally proceeds thereafter to a step offorming the gate insulation films of MISFETs other than the MISFETshaving a high withstand voltage, according to the present mode forcarrying out the invention, a process as described below (hereinafterreferred to as a “fourth process”) may be performed in addition to saidfirst process, second process or third process in order to set the Vthof said driving MISFETs, transfer MISFETs and MISFETs for loadresistance relatively and intentionally higher than the Vth ofpredetermined MISFETs of the SRAM peripheral circuits and logiccircuits.

[0096] First, an oxidation process for forming the gate insulation filmsof MISFETs forming memory cells and MISFETs for which any leakagecurrent between the source and drain must be suppressed is carried outto form gate insulation films having an intermediate relative thicknessof, for example, about 5 nm on the principle surface of thesemiconductor substrate 3. The thickness of the gate insulation films ismade greater than the thickness of gate insulation films formed onregions to form MISFETs whose operating speed must be increased in theregions of peripheral circuits and logic circuits. This makes itpossible to relatively and intentionally increase the Vth of the MISFETsforming memory cells and said MISFETs for which any leakage current mustbe suppressed.

[0097] Subsequently, a photoresist pattern is formed on the gateinsulation films having an intermediate thickness to cover regions toform said MISFETs for which any leakage current must be suppressed inthe entire memory cell region, peripheral circuit regions and logiccircuit regions and to expose other regions; and, thereafter, the gateinsulation films having an intermediate thickness exposed from thephotoresist pattern are removed and the photoresist pattern is removedfurther.

[0098] Thereafter, an oxidation process for forming the gate insulationfilms of MISFETs which must operate at a high speed on the semiconductorsubstrate 3 is performed to form gate insulation films having theminimum relative thickness less than, for example, 5 nm on the principlesurface of the semiconductor substrate 3.

[0099] Next, as shown in FIG. 11, a conductive film 18 for forming-gateelectrodes is formed on the semiconductor substrates using a CVD processor the like to cover gate insulation films 17 formed as described aboveand the upper surface of the isolation portions 4. For example, theconductive film 18 is constituted by a single film made of lowresistance polysilicon, a multi-layer film formed by coating lowresistance polysilicon with a tungsten silicide film or a multi-layerfilm formed by coating low resistance polysilicon with a metal film suchas tungsten with a barrier metal film such as tungsten nitride ortitanium nitride interposed therebetween. Said barrier metal filmfunctions as a barrier layer for preventing the tungsten film andpolysilicon film from reacting to each other during a high temperaturethermal process to form a high resistance silicide layer at theinterface between them.

[0100] Subsequently, a photoresist pattern 12E is formed on theconductive film 18 to expose regions to form n-channel type MISFETs inthe memory cell region and other regions and to cover other regions,and, for example, phosphorus ions are implanted into the conductive film18 using it as a mask. Thereafter, after removing the photoresistpattern 12E, a capping insulation film made of, for example, siliconoxide or silicon nitride is deposited on the conductive film 18 using aCVD process or the like.

[0101] Next, after patterning the capping insulation film with-aphotoresist pattern as a mask using a dry etching process or the like,the photoresist pattern is removed; the conductive film 18 is patternedusing the patterned capping insulation film as a mask; and the cappinginsulation film 19 is removed further to form gate electrodes 6g asshown in FIG. 12. The capping insulation film and the conductive film 18are patterned at one time using a photolithographic technique and a dryetching technique to form the gate electrodes 6g (6gd, 6gL) and thecapping insulation film. In this case, the capping insulation film isleft on the gate electrodes 6g. The minimum gate length for the gateelectrodes 6g is set at a minimum dimension (for example, 0.24μ) withina tolerance in which the short channel effect of MISFETs can besuppressed to maintain the Vth of the same at a predetermined value ormore.

[0102] Next, for example, phosphorus (P) ions are implanted into thep-wells 16PW using a photoresist pattern as a mask as shown in FIG. 13to form n-type semiconductor regions 5 a in the p-wells 16PW on bothsides of the gate electrodes 6g.

[0103] While the n-type semiconductor regions 5 a are not formed at thisstage because no thermal process for activation and the like has beenperformed, they are shown here for better understanding of thedescription.

[0104] Subsequently, after removing the photoresist pattern, forexample, boron (B) ions are implanted into the n-wells 16NW using anewly formed photoresist pattern 12F as a mask to form p-typesemiconductor regions 7 a in the n-wells 16NW on both sides of the gateelectrodes 6g. While the p-type semiconductor regions 7 a are not formedat this stage because no thermal process for activation and the like hasbeen performed, they are shown here for better understanding of thedescription.

[0105] Next, after removing the photoresist pattern 12F, a thermalprocess is carried out for the activation of the impurities introducedinto the semiconductor substrates; as shown in FIG. 14, a siliconnitride film having a thickness of about 50 nm is deposited thereafteron the semiconductor substrate 3 using a CVD process or the like; andthe silicon nitride film is then subjected to anisotropic etching toform side walls spacers 19 on the side walls of the gate electrodes 6g.This etching is carried out using an etching gas that promotes theetching of a silicon nitride film at a rate greater than that for asilicon oxide film in order to minimize the amount of removal of thegate insulation films 17 and the silicon oxide films buried in theisolation portions 4. When the capping insulation film constituted by asilicon nitride film is formed on the gate electrodes 6g, the amount ofoveretching is also limited to the required minimum in order to minimizethe amount of removal of the same.

[0106] Next, for example, arsenic (A) ions are implanted into thep-wells 16PW using a photoresist pattern as a mask to form n⁺-typesemiconductor regions 5 b of n-channel type MISFETS. While the n⁺-typesemiconductor regions 5 b are not formed at this stage because nothermal process for activation and the like has been performed, they areshown here for better understanding of the description. The n-typesemiconductor regions 5 shown in FIG. 3, for example, are constituted bythe n-type semiconductor regions 5 a and n⁺-type semiconductor regions 5b.

[0107] Subsequently, after removing the photoresist pattern, forexample, boron (B) ions are implanted into the n-wells 16NW using anewly formed photoresist pattern 12G as a mask to form p⁺-typesemiconductor regions 7 b of p-channel type MISFETs.

[0108] While the p⁺-type semiconductor regions 7 b are not formed atthis stage because no thermal process for activation and the like hasbeen performed, they are shown here for better understanding of thedescription. The p-type semiconductor regions 7 shown in FIG. 3, forexample, are constituted by the p-type semiconductor regions 7 a andp⁺-type semiconductor regions 7 b.

[0109] Next, after removing the photoresist pattern 12G, a thermalprocess is carried out for the activation of the impurities introducedinto the semiconductor substrate 3 to form p-channel type MISFETs Qp, QLand n-channel type MISFETs Qn, Qd.

[0110] Next, a conductive film made of titanium nitride (TiN), cobalt(Co) or the like is deposited on the semiconductor substrate 3 using asputtering process or the like, and a thermal process is performedthereafter to form a silicide layer 20 at the interface between theconductive film and the semiconductor substrate 3 and the gateelectrodes 6g as shown in FIG. 15. Subsequently, a thermal process isperformed again after removing the conductive film which has not beensilicified.

[0111] Next, an insulation film 21 a constituted by a silicon nitridefilm or the like is deposited on the semiconductor substrate 3 using aCVD process or the like; an insulation film 21 b made of PSG (phoshosilicate glass) is deposited thereon using a CVD process or the like;and an insulation film 21 c made of, for example, silicon oxide isfurther deposited thereon. Subsequently, after planarizing the uppersurface of the insulation film 21 c using a CMP process, connectionholes 8 are formed in a part of the insulation films 21 a-21 c.Thereafter, for example, titanium, titanium nitride and tungsten aredeposited on the semiconductor substrate 3 in the older of precedence instacking and are etched back thereafter using a CMP process to bury andform conductive films 22 in the connection holes 8.

[0112] Next, for example, titanium, aluminum or an aluminum alloy,titanium and titanium nitride are deposited on the semiconductorsubstrate 3 in the order of precedence in stacking and are thereafterpatterned using a photolithographic technique and a dry etchingtechnique to form first layer wiring 9L. Subsequently, second layerwiring 23L and third layer wiring 24L are formed similarly to said firstlayer wiring 9L. Reference numbers 21 d, 21 e represent, for example,insulation films made of silicon oxide. A normal method of manufacturinga semiconductor integrated circuit device is hereafter used tomanufacturers microprocessor incorporating an.SRAM for a cache memory.

[0113] The effects of the present mode for carrying out the inventionwill now be described with reference to FIGS. 18 through 20.

[0114]FIG. 18 shows a transfer curve in a case wherein the Vth ofMISFETs forming memory cells is relatively and intentionally increasedas in the present mode for carrying out the invention, and FIG. 19 showsa transfer curve in a case wherein the Vth is not increased. FIG. 20shows an SNM for the Vth of driving MISFETs.

[0115] As apparent from a comparison between the transfer curves inFIGS. 18 and 19, the present mode for carrying out the invention makesit possible to improve an SNM significantly. Especially, as apparentfrom FIGS. 18 through 20, when the first process or second process isperformed to increase the Vth of driving MISFETs, the SNM is abruptlyincreased and a sufficient operational margin can be maintained for thememory cells.

[0116] Thus, the following effects can be achieved by the mode 1 forcarrying out the invention.

[0117] (1) In a microprocessor incorporating an SRAM, since the Vth ofdriving MISFETs, transfer MOSFETs and MISFETs for load resistance formemory cells of the SPAM is relatively and intentionally increased, theSNM of the SRAM can be improved while improving the operating speed ofthe microprocessor, reducing the power supply voltage (i.e., reducingthe power consumption) and improving the degree of element integrationas a result of the use of a groove type isolation structure.

[0118] (2) It is possible to reduce the rate of occurrence of readfaults and write faults of the memory in the microprocessorincorporating an-SRAM.

[0119] (3) According to the above effects (1), (2), it is possible toimprove the reliability of the operation of a microprocessorincorporating an SRAM which is compact, which has high performance andwhich can operate at a high speed with a small power consumption.

[0120] Embodiment 2:

[0121]FIG. 21 is a plan view of major parts of a semiconductorintegrated circuit device which represents another mode for carrying outthe invention taken during the manufacture of the same.

[0122] While the mode 1 for carrying out the invention involves a casein which the Vth of all MISFETs that form memory cells of an SRAM isrelatively and intentionally increased, the invention is not limitedthereto, and the Vth of predetermined MISFETs of the memory cells of theSRAM may be relatively and intentionally increased.

[0123] The mode 2 for Carrying out the invention describes it and, forexample, in order to increase the Vth of transfer MISFETs relatively andintentionally, a photoresist pattern 12A2 may be formed on thesemiconductor substrate 3 as shown in FIG. 21 instead of the photoresistpattern 12A shown in FIG. 6 at said first process or second processdescribed in said mode 1 for carrying out the invention, such thatregions to form the transfer MISFETs are exposed and other regions arecovered. FIG. 21 shows the same memory cell region as in FIGS. 3, 6 andothers and shows elements and the like for clearly showing the positionwhere the photoresist pattern 12A2 is formed as in the abovedescription. The photoresist pattern 12A2 is also hatched in FIG. 21 forbetter clarity of the figure. Further, the configuration of thephotoresist pattern 12A2 is not limiting aspect of the presentinvention; and, for example, the pattern may be formed in aconfiguration which exposes regions to form the transfer MISFETs Qt andregions to form n-channel type MISFETs formed in the semiconductorsubstrate 3, especially regions to form MISFETs for which any leakagecurrent between the source and drain must be suppressed and which coversother regions. According to such a mode 2 for carrying out theinvention, especially, it is possible to reduce the rate of occurrenceof read faults of a memory while improving the operating speed of amicroprocessor incorporating an SRAM, reducing the power supply voltage(i.e., reducing the power consumption) and improving the degree ofelement integration. It is therefore possible to improve the reliabilityof the operation of a microprocessor incorporating an SRAM which iscompact, which has high performance and which a can operate at a highspeed with small power consumption.

[0124] Embodiment 3:

[0125]FIG. 22 is a plan view of major parts of a semiconductorintegrated circuit device which represents another mode for carrying outthe invention taken during the manufacture of the same.

[0126] The mode 3 for carrying out the invention involves a case whereinthe Vth of driving MISFETs is to be relatively and intentionallyincreased. In this case, a photoresist pattern 12A3 may be formed on thesemiconductor substrate 3, as shown in FIG. 22, instead of thephotoresist pattern 12A (see FIG. 6) at said first process or secondprocess described in said mode 1 for carrying out the invention, suchthat regions to form the driving MISFETs are exposed and other regionsare covered. FIG. 22 also shows the same memory cell region as in Pigs.3, 6 and others and shows elements and the like for clearly showing theposition where the photoresist pattern 12A3 is formed h in the abovedescription. The photoresist pattern 12A3 is also hatched in FIG. 22 forbetter clarity of the figure. Further, the configuration of thephotoresist pattern 12A3 is not a limiting aspect of the presentinvention; and, for example, the pattern may be formed in aconfiguration which exposes regions to form the driving MISFETs Qd andregions to form n-channel type MISFETs formed in the semiconductorsubstrate 3, especially regions to form MISFETs for which any leakagecurrent between the source and drain must be suppressed, and whichcovers other regions.

[0127] According to such a mode 3 for carrying out the invention,especially, it is possible to improve the SNM of an SRAM while improvingthe operating speed of a microprocessor incorporating an SRAM, reducingthe power supply voltage (i.e., reducing the power consumption) andimproving the degree of element integration. It is therefore possible toimprove the reliability of the operation of a microprocessorincorporating an SRAM which can operate at a high speed with small powerconsumption.

[0128] Embodiment 4:

[0129]FIGS. 23 through 25 are plan views of major parts of asemiconductor integrated circuit device which represents another modefor carrying out the invention taken during the manufacture of the same.

[0130] The mode 4 for carrying out the invention describes amodification of the third process described in said mode 1 for carryingout the invention. Specifically, while said third process involves acase wherein nitrogen is introduced into a semiconductor substrate usingion implantation, nitrogen is segregated on the interface between gateinsulation films and a semiconductor substrate by mixing nitrogen gas inthe atmosphere of a thermal process in the mode 4 for carrying out theinvention, and the specific method for the same is as follows.

[0131] First, as shown in FIG. 23, gate insulation films 17 made of, forexample, silicon oxide are formed on the principle surface of aSemiconductor substrate 3 using a normal gate oxidation process; aphotoresist pattern 12H is formed on the principle surface of thesemiconductor substrate 3 to cover the memory cell region and to exposeother regions; and the gate insulation films 17 exposed therefrom areremoved using it as an etching mask.

[0132] The photoresist pattern 12H is then removed to leave the gateinsulation films 17 only in the memory cell region as shown in FIG. 24.Thereafter, a gate oxidation process is performed on the semiconductorsubstrate 3, for example, in an NO (nitrogen oxide) or N₂O (nitrogenmonoxide) atmosphere to form the gate insulation films 17 (17 a, 17 b)as shown in FIG. 25. Thus, nitrogen is segregated on the interfacebetween the gate insulation films 17 and the semiconductor substrate 3(nitrogen oxide process).

[0133] In this case, since the gate insulation film 17 a in the memorycell region is thicker than the gate insulation film 17 b in otherregions, the concentration of nitrogen is relatively higher in thethinner gate insulation film 17 b than in the thicker gate insulationfilm 17 a. As a result, the Vth of MISFETs formed in the memory cellregion can be made relatively, and intentionally higher than the Vth ofMISFETs formed in other regions. Further description will be omittedbecause it will be the same as that for said mode 1 for carrying out theinvention.

[0134] Such a mode 4 of carrying out the invention makes it possible toachieve the same effects as those available in the mode 1 for carryingout the invention.

[0135] While the invention conceived by the inventor has beenspecifically described based on modes for carrying out the same, theinvention is not limited to said modes for carrying out the inventionand may obviously be modified in various ways without departing from theprinciple thereof.

[0136] For example, the semiconductor wafer is not limited to singlefilms made of silicon single crystals and may be modified in variousways. For example, an epitaxial wafer may be used which is obtained byforming a thin epitaxial layer (of 1 μm, for example) on the surface ofa semiconductor substrate made of silicon single crystals, and,alternatively, an SOI (silicon on insulator) wafer may be used which isobtained by providing a semiconductor layer for forming elements on aninsulated layer.

[0137] While the above description has been made on applications, of theinvention made by the inventor to microprocessors incorporating SRAMmemory cells which involve the field of application that is thebackground of the invention, the invention is not limited thereto andmay be applied to, for example, semiconductor integrated circuit devicesand the like constituted solely by an SRAM. Further, while said modesfor carrying out the invention have referred to the use of six MISFETtype SRAM cells, the invention is not limited thereto, and, for example,it is possible to use high resistance load type SRAM cells utilizingpolysilicon resistors as load resistance elements and SRAM cells havingthe so-called TFT structure in which two polysilicon layers are providedon driving MISFETs to form a p-channel type MOSFET used as a loadresistance element with the polysilicon layers. It may also be appliedto semiconductor devices in which MISFETs forming an SRAM and othercircuits, and bipolar transistors are formed on a semiconductorsubstrate.

[0138] Effects provided by typical aspects of the invention disclosed inthe present specification can be briefly described as follows.

[0139] (1) The present invention makes it possible to improve the staticnoise margin (SNM) of an SRAM while improving the operating speed of amicroprocessor incorporating an SRAM and reducing the power supplyvoltage of the same (i.e., reducing the power consumption).

[0140] (2) The present invention makes it possible to reduce the rate ofoccurrence of read faults and write faults of a memory of amicroprocessor incorporating an SRAM.

[0141] (3) According to the above effects (1), (2), it is possible toimprove the reliability of operation of a microprocessor incorporatingan SRAM which can operate at a high speed with small power consumption.

1-25 (cancelled)
 26. A method for manufacturing a semiconductorintegrated circuit device including a memory cell of an SRAM having afirst p-channel MISFET and a first n-channel MISFET, and a peripheralcircuit having a second p-channel MISFET and a second n-channel MISFET,comprising: providing a silicon on insulator substrate including aninsulated layer and a semiconductor layer formed on said insulatedlayer, wherein said semiconductor layer has a memory cell forming regionand a peripheral circuit forming region, wherein said memory cellforming region includes a first p-channel MISFET forming region wheresaid first p-channel MISFET is to be formed and a first n-channel MISFETforming region where said first n-channel MISFET is to be formed,wherein said peripheral circuit forming region includes a secondp-channel MISFET forming region where said second p-channel MISFET is tobe formed and a second n-channel MISFET forming region where said secondn-channel MISFET is to be formed; selectively introducing a firstimpurity into said first p-channel MISFET forming region and said secondp-channel MISFET forming region for controlling a threshold voltage;selectively introducing a second impurity into said first n-channelMISFET forming region and said second n-channel MISFET forming regionfor controlling a threshold voltage; selectively introducing a thirdimpurity into said first p-channel MISFET forming region by using a maskcovering said second p-channel MISFET forming region for controlling athreshold voltage such that a threshold voltage of said first p-channelMISFET is higher than a threshold voltage of said second p-channelMISFET; and selectively introducing a fourth impurity into said firstn-channel MISFET forming region by using a mask covering said secondn-channel MISFET forming region for controlling a threshold voltage suchthat a threshold voltage of said first n-channel MISFET is higher than athreshold voltage of said second n-channel MISFET.
 27. A method formanufacturing a semiconductor integrated circuit device according toclaim 26, further comprising: forming a groove in said semiconductorlayer for defining said first p-channel MISFET forming region, saidfirst n-channel MISFET forming region, said second p-channel MISFETforming region and said second n-channel MISFET forming region; andburying an insulating film in said groove by polishing an insulatingfilm formed over said substrate having said groove.
 28. A method formanufacturing a semiconductor integrated circuit device according toclaim 26, further comprising: forming gate electrodes of said firstn-channel MISFET, said first p-channel MISFET, said second n-channelMISFET and said second p-channel MISFET; and forming a source and drainregion of said first n-channel MISFET, said first p-channel MISFET, saidsecond n-channel MISFET and said second p-channel MISFET.
 29. A methodof manufacturing a semiconductor integrated circuit device, comprising:providing a silicon on insulator substrate including an insulated layerand a semiconductor layer formed on said insulated layer, wherein saidsemiconductor layer has a memory cell of SRAM having a first p-channelMISFET and a first n-channel MISFET, and a logic circuit for amicroprocessor having a second p-channel MISFET and a second n-channelMISFET, wherein said first p-channel MISFET is formed at a firstp-channel MISFET forming region of said semiconductor layer, whereinsaid first n-channel MISFET is formed at a first n-channel MISFETforming region of said semiconductor layer, wherein said secondp-channel MISFET is formed at a second p-channel MISFET forming regionof said semiconductor layer, wherein said second n-channel MISFET isformed at a second n-channel MISFET forming region of said semiconductorlayer; selectively introducing a first impurity into said firstp-channel MISFET forming region and said second p-channel MISFET formingregion for controlling a threshold voltage; selectively introducing asecond impurity into said first n-channel MISFET forming region and saidsecond n-channel MISFET forming region for controlling a thresholdvoltage; selectively introducing a third impurity into said firstp-channel MISFET forming region by using a mask covering said secondp-channel MISFET forming region for controlling a threshold voltage suchthat a threshold voltage of said first p-channel MISFET is higher than athreshold voltage of said second p-channel MISFET; selectivelyintroducing a fourth impurity into said first n-channel MISFET formingregion by using a mask covering said second n-channel MISFET formingregion for controlling a threshold voltage such that a threshold voltageof said first n-channel MISFET is higher than a threshold voltage ofsaid second n-channel MISFET; forming a groove in said semiconductorlayer for defining said first p-channel MISFET forming region, saidfirst n-channel MISFET forming region, said second p-channel MISFETforming region and said second n-channel MISFET forming region; andburying said groove with an insulating film by polishing an insulatingfilm formed over said semiconductor layer having said groove.
 30. Amethod of manufacturing a semiconductor integrated circuit deviceaccording to claim 29, wherein an operating speed thereof is 100 MHz ormore.
 31. A method of manufacturing a semiconductor integrated circuitdevice, comprising: providing a silicon on insulator substrate includingan insulated layer and a semiconductor layer formed on said insulatedlayer, wherein said semiconductor layer has a memory cell of an SRAMhaving a first p-channel MISFET and a first n-channel MISFET, and aperipheral circuit having a second p-channel MISFET and a secondn-channel MISFET, wherein said first p-channel MISFET is formed at afirst p-channel MISFET forming region of said semiconductor layer,wherein said first n-channel MISFET is formed at a first n-channelMISFET forming region of said semiconductor layer, wherein said secondp-channel MISFET is formed at a second p-channel MISFET forming regionof said semiconductor layer, wherein said second n-channel MISFET isformed at a second n-channel MISFET forming region of said semiconductorlayer; selectively introducing a first impurity into said firstp-channel MISFET forming region and said second p-channel MISFET formingregion for controlling a threshold voltage; selectively introducing asecond impurity into said first n-channel MISFET forming region and saidsecond n-channel MISFET forming region for controlling a thresholdvoltage; selectively introducing a third impurity into said firstp-channel MISFET forming region by using a mask covering said secondp-channel MISFET forming region for controlling a threshold voltage suchthat a threshold voltage of said first p-channel MISFET is higher than athreshold voltage of said second p-channel MISFET; and selectivelyintroducing a fourth impurity into said first n-channel MISFET formingregion by using a mask covering said second n-channel MISFET formingregion for controlling a threshold voltage such that a threshold voltageof said first n-channel MISFET is higher than a threshold voltage ofsaid second n-channel MISFET; forming a groove in said semiconductorlayer for defining said first p-channel MISFET forming region, saidfirst n-channel MISFET forming region, said second p-channel MISFETforming region and said second n-channel MISFET forming region; andburying said groove with an insulating film by polishing an insulatingfilm formed over said semiconductor layer having said groove.
 32. Amethod of manufacturing a semiconductor integrated circuit deviceaccording to claim 31, wherein an operating speed thereof is 100 MHz ormore.
 33. A method of manufacturing a semiconductor integrated circuitdevice including a memory cell of an SRAM having a first p-channelMISFET and a first n-channel MISFET, and a peripheral circuit having asecond p-channel MISFET and a second n-channel MISFET, comprising: (a)providing a semiconductor substrate having a memory cell forming regionand a peripheral circuit forming region, wherein said memory cellforming region includes a first p-channel MISFET forming region wheresaid first p-channel MISFET is to be formed and a first n-channel MISFETforming region where said first n-channel MISFET is to be formed,wherein said peripheral circuit forming region includes a secondp-channel MISFET forming region where said second p-channel MISFET is tobe formed and a second n-channel MISFET forming region where said secondn-channel MISFET is to be formed; (b) selectively introducing a firstimpurity into said first p-channel MISFET forming region and said secondp-channel MISFET forming region for controlling a threshold voltage; (c)selectively introducing a second impurity into said first n-channelMISFET forming region and said second n-channel MISFET forming regionfor controlling a threshold voltage; (d) selectively introducing a thirdimpurity into said first p-channel MISFET forming region by using a maskcovering said peripheral circuit forming region for controlling athreshold voltage such that a threshold voltage of said first p-channelMISFET is higher than threshold voltages of said second p-channel MISFETand said further MISFET; (e) introducing a fourth impurity into saidfirst n-channel MISFET forming region by using a mask covering saidperipheral circuit forming region for controlling a threshold voltagesuch that a threshold voltage of said first n-channel MISFET is higherthan threshold voltages of said second n-channel MISFET and said furtherMISFET; (f) forming a mask pattern for exposing a first region where aMISFET having a relatively higher operating speed is to be formed insaid peripheral circuit, wherein said mask pattern covers said memorycell forming region and a second region in said peripheral circuitforming region where a MISFET is to be formed; and (g) introducing afifth impurity into said first region of said peripheral circuit formingregion by using said mask pattern as a mask for controlling a thresholdvoltage such that a threshold voltage of said MISFET to be formed insaid first region is lower than a threshold voltage of said MISFET to beformed in said second region.
 34. A method of manufacturing asemiconductor integrated circuit device according to claim 33, includingforming gate insulating films for said MISFET to be formed in said firstregion and said MISFET to be formed in said second region wherein athickness of a gate insulating film of said MISFET formed in said firstregion is thinner than a gate insulating film of said MISFET formed insaid second region.
 35. A method of manufacturing a semiconductorintegrated circuit device according to claim 33, further comprising:forming a groove in said substrate for defining said first p-channelMISFET forming region, said first n-channel MISFET forming region, saidsecond p-channel MISFET forming region, said second n-channel MISFETforming region and said further MISFET forming region; and burying aninsulating film in said groove by polishing an insulating film formedover said substrate having said groove.